1. Field of the Invention
The present invention relates to a wiring board and a method for manufacturing the same, and more particularly to an embedded wiring board and a method for manufacturing the same.
2. Related Art
In the current wiring board technology, an embedded wiring board is developed, in which a wiring on a surface thereof is buried in a dielectric layer instead of protruding from a surface of the dielectric layer.
FIG. 1 is a cross-sectional view of a conventional embedded wiring board. Referring to FIG. 1, the conventional embedded wiring board 100 includes a dielectric layer 110, two wiring layers 120a and 120b, and a conductive pillar 130. The dielectric layer 110 has an upper surface 112 and a lower surface 114 opposite to each other, a blind via T1, and a recess S1 on the upper surface 112, and the wiring layers 120a and 120b are respectively buried in the upper surface 112 and the lower surface 114.
The wiring layer 120a includes at least one pad 122a and a plurality of traces 124a, and the wiring layer 120b includes at least one pad 122b and a plurality of traces 124b. The pad 122a is disposed in the recess S1, and the conductive pillar 130 is disposed in the blind via T1 and is connected between the pad 122a and the pad 122b. As such, the wiring layers 120a and 120b are electrically connected to each other.
The pad 122a and the conductive pillar 130 are usually formed by a metal layer 102 and a plating deposit 104, and the traces 124a are formed by a metal layer 106 and a plating deposit 108. The metal layer 102 covers all surfaces of the recess S1 and the blind via T1, and the plating deposit 104 is located on the metal layer 102. The metal layer 102 and the plating deposit 104 fill up the recess S1 and the blind via T1, so as to form the pad 122a and the conductive pillar 130.
Generally, the metal layers 102 and 106 are mostly formed through electroless plating, and the plating deposit 104 and the plating deposit 108 are usually formed through electrical plating. Particularly, no external current is applied during the process for forming the metal layers 102 and 106, and the plating deposit 104 and the plating deposit 108 are formed by applying an external current.
Accordingly, the manner of forming the metal layers 102 and 106 is different from the manner of forming the plating deposit 104 and the plating deposit 108, such that an interface F1 exists between the metal layer 102 and the plating deposit 104, and an interface F2 exists between the metal layer 106 and the plating deposit 108. After the embedded wiring board 100 is sliced, the interfaces F1 and F2 can be observed by using an optical microscope.
In order to form the metal layers 102 and 106, a seed layer (not shown in FIG. 1) is usually firstly formed on the upper surface 112 of the dielectric layer 110, in the recess S1, and in the blind via T1, and the seed layer is usually an activated palladium layer. The seed layer has an oxidation and reduction reaction with chemical solutions for forming the metal layers 102 and 106, so as to reduce metal ions in the chemical solutions, thereby forming the metal layers 102 and 106. Thus, the embedded wiring board 100 is manufactured.